Each memory cell of a semiconductor memory system, such as a memory device, has traditionally been used to store one binary digit (“bit”) of digital information. In order to store large amounts of digital information large arrays of memory cells are used. One challenge that is presented by the traditional approach of one bit per cell is to continually shrink the size of the memory array in order to increase the capacity of the memory without dramatically increasing the overall size of the memory system. Example approaches to reduce the size of the array have been to design memory cells that occupy less area and reducing the distance between the memory cells in order to increase memory cell density and capacity. As the feature size of the memory cells becomes smaller, however, the complexity of fabricating the memory increases resulting in increased cost of manufacturing.
A relatively recent approach to increasing memory capacity has been to design memory cells and supporting circuitry for storing multiple bits of digital information in each memory cell. For example, rather than store one bit of digital information, as has been the tradition, two bits of digital information are stored by a memory cell. Storage of two bits of digital information is accomplished by having memory cells and read/write circuitry that can accurately store, read, and write four distinct memory states. Each of the four memory states represents a different combination of two bits of information, that is, 00, 01, 10, and 11. In contrast, the traditional one bit per cell approach requires memory cells and read/write circuitry that can accurately store, read, and write two distinct memory states, each distinct memory state representing either a 0 or 1. Use of memory cells for storing more than two memory states may be applicable for different types of memory, for example, in both volatile (e.g., DRAM) and non-volatile memory (e.g., flash memory).
Projecting forward along the current trajectory of using memory cells for storing more than two memory states, starting with using two different memory states for storing one bit of digital information and evolving to using four different memory states for storing two bits of digital information, three bits of digital information may be stored by using eight different memory states and four bits of digital information may be stored by using sixteen different memory states. As illustrated by this example, the number of memory states per memory cell is a power-of-two, and the resulting number of bits stored per cell is the base two logarithm of the number of memory states.
A challenge with designing memory systems along this trajectory is the difficulty of reliably and accurately storing, reading, and writing, for example, twice as many memory states as the previous iteration. Evolving from storing, reading and writing two memory states to storing, reading and writing four memory states presented difficulties that were eventually overcome. Evolving from using four memory states to using eight memory states, however, presents challenges that are much more difficult with the current state of technology than those presented in the previous evolution of two memory states to four memory states. Although the difficulties are not insurmountable and will eventually be overcome, it is desirable to have, for example, memory systems utilizing memory cells for storing multiple memory states to provide a storage density of greater than one bit per cell without being limited to storing a power-of-two number of memory states.